TITLE: Enabling Hyperscale Web Services
Current hardware and software systems were conceived at a time when we had scarce compute and memory resources, limited quantity of data and users, and easy hardware performance scaling due to Moore’s Law. These assumptions are not true today. Today, emerging web services require data centers that scale to hundreds of thousands of servers, i.e., hyperscale, to efficiently process requests from billions of users. In this new era of hyperscale computing, we can no longer afford to build each layer of the systems stack separately. Instead, we must rethink the synergy between the software and hardware worlds from the ground up.
In this talk, I will focus on re-thinking (1) software threading and concurrency paradigms and (2) data center hardware architectures. First, I will describe μTune, my software threading framework that is aware of the overheads induced by the underlying hardware’s constraints. Then, I will discuss SoftSKU and Accelerometer—my proposals to answer the question of: How should we build data center hardware for emerging software paradigms in the post-Moore era? Finally, I will conclude by describing my ongoing and future research towards re-designing the systems stack to enable the hyperscale web services of tomorrow.
Akshitha Sriraman is a Ph.D. candidate in Computer Science and Engineering at the University of Michigan. Her research bridges computer architecture and software systems, demonstrating the importance of that bridge in realizing efficient hyperscale web services via solutions that span the systems stack. Her systems solutions to improve hardware efficiency have been deployed in real hyperscale data centers and currently serve billions of users, saving millions of dollars and meaningfully reducing the global carbon footprint. Additionally, her hardware design proposals have influenced Intel’s Alder Lake+ CPU architectures.
Sriraman has been recognized with a Facebook Fellowship, a Rackham Merit Ph.D. Fellowship, and was selected for the Rising Stars in EECS Workshop. Her work has been recognized with an IEEE Micro Top Picks distinction and has appeared in top architecture and systems venues like OSDI, ISCA, ASPLOS, MICRO, and HPCA.
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